1. Field of the Invention
The present invention relates to a method of fabricating a buried contact structure used in MOS and bipolar (including BiMOS or BiCMOS) semiconductor devices, and more particularly to a method of fabricating a buried contact structure by using WSi.sub.x spacers as an etching stop during the process of defining a gate electrode so as to prevent the formation of ditches in a substrate.
2. Description of the Related Art
Buried contacts have been extensively used in MOS or bipolar integrated circuits. For example, buried contacts are used in a MOS SRAM (static random-access memory) cell, which employs two loads (active load or passive load) and two cross-coupled MOS transistors, to connect each gate electrode to the drain region of the opposing cross-coupled MOS transistors. In a typical memory cell architecture, the buried contacts are also electrically connected to source/drain regions of MOS transistors, which form transmission-gates to provide data paths into or out of the memory cell. Consequently, buried contacts provide electrical interconnection among gate electrodes, drain regions of the cross-coupled MOS transistors and source/drain regions of the transmission-gate transistors.
A conventional process for the formation of buried contacts is depicted in FIGS. 1A through 1D, which are cross-sectional views along line I--I of FIG. 2. Referring to FIG. 1A, field oxide 11 is first formed on P-type semiconductor substrate 10 as an isolating structure so as to define active region 12 (as shown in FIG. 2) bounded thereby.
As well known in this art, field oxides 11 are formed by a so-called LOCOS (local oxide of silicon) process. Then, gate oxide layer 13 is thermally grown on the surface of substrate 10 not covered by field oxides 11. First polysilicon layer 14a is then deposited on field oxides 11 and gate oxide layer 13. Thereafter, first polysilicon layer 14a and gate oxide layer 13 are patterned and etched to form opening 15 to expose a portion of substrate 10.
Referring to FIG. 1B, second polysilicon layer 14b is conformably deposited over exposed substrate 10 via opening 15 and first polysilicon layer 14a. After that, impurities, such as N-type ions (e.g., phosphorus ions), are implanted into second polysilicon layer 14b to increase the conductivity thereof. After thermal annealing is performed, the implanted impurities contained in second polysilicon layer 14b are diffused into substrate 10 to form N-type heavily-doped region 25, designated as N.sup.+ in the drawing. Then, photoresist layer 16 with gate and interconnect patterns is formed on second polysilicon layer 14b.
Next, referring to FIG. 1C, by utilizing photoresist layer 16 as a mask, second polysilicon layer 14b and first polysilicon layer 14a are subsequently etched to define transistor's gate electrode 17 and interconnect layer 18. Note that ditch 23 will be inevitably formed in substrate 1 during the etching process used to define gate electrode 17 and interconnect layer 18. This ditch formation occurs since there is poor substrate/polysilicon etch selectivity (the ratio of etching rates of different materials is known as the etching selectivity of an etch process) and no gate oxide layer 13 is provided within the region of opening 15 as an etching stop. As a result, the reactive ion etch gases used to etch polysilicon layers 14a and 14b also etch the single crystal silicon substrate 10 at about the same rate. Photoresist layer 16 is thereafter removed.
As next shown in FIG. 1D, another N-type ion implantation is applied to create N-type lightly-doped source drain regions 20 in substrate 10. Then, by chemical vapor deposition, an oxide layer is formed onto the overall surface. The CVD oxide layer is then removed by an etchback process to form oxide spacers 21 which remain on the sidewalls of gate electrode 17 and interconnect layer 18. Next, the other N-type ion implantation (e.g., implanting arsenic ions), which uses a higher implantation dose than that used for forming lightly-doped source/drain regions 20, is applied to form N-type heavily-doped source/drain regions 22 in substrate 10 to finish the process. The resulting structure depicted in FIG. 2 is a conventional buried contact structure in top view.
However, lattice defects, such as dislocation loops or the like, are formed around ditch 23, which cause a leakage current therethrough. Moreover, inevitably formed ditch 23 causes spacers 21 within opening 15 to thicken, thus reducing the dosage of impurities implanted in underlying heavily-doped source/drain region 22. This accordingly increases the resistance and thus induces the resistance deviation of heavily-doped region 22. Ditch 23 also results in poor step coverage in the subsequent process steps, for example in the deposition of pre-metal dielectric layer such as BPSG (borophosphosilicate glass), thus reducing the reliability of the resulting semiconductor devices.